1. Field of the Invention
The present invention generally relates to a driving method for a liquid-crystal-display (LCD), and more particularly, to a driving method utilizing a gate expiatory voltage and a capacitor coupling effect to drive the LCD by a thin-film-transistor (TFT) active matrix. The present invention can simplify gate pulse waveforms generated by a gate driving circuit, lessen the output voltage range generated by a video signal driving circuit and significantly reduce the difficulty and cost for circuit design.
2. Description of the Related Art
FIG. 1 is a driving circuit with a TFT active matrix disclosed in U.S. Pat. No. 5,296,847. The driving circuit with a TFT active matrix comprises a TFT matrix 10, a scanning channel driving circuit 11, a video channel driving circuit 12, and a constant voltage generating circuit 13. Each TFT in the TFT matrix 10 connects to a storage capacitor Cs to drive a relative LCD cell (shown as a loading capacitor Clc). The scanning channel driving circuit 11 generates gate controlling signals Vg(N), Vg(Nxe2x88x921) . . . to drive the gates of the connected TFTs via scanning channels 11a, 11b. . . The video channel driving circuit 12 generates and sends video signals to the LCD cells via video signal channels 12a, 12b. . . and the TFTs. The constant voltage generating circuit 13 generates a constant voltage Vt as a reference voltage for all LCD cell Clc.
FIG. 2 is an enlarged diagram of the area 10xe2x80x2 in FIG. 1. In this prior art, the TFT is positioned at the intersection of the video signal channel 12b and the scanning channel 11b. Three parasitic capacitors of Cgd, Csd and Cgs are formed between gate/drain, source/drain and gate/source respectively. The gate of the TFT connects to a gate controlling signal Vg(N) for scanning, the source of the TFT connects to a video signal Vsig, and the drain of the TFT, a pixel electrode of a LCD cell, connects to a terminal of a storage capacitor Cs and a terminal of a LCD cell. The other terminal of the storage capacitor Cs connects to a preceding gate controlling signal Vg(Nxe2x88x921) in a preceding (first) scanning channel. The other terminal of the LCD cell Clc connects to a reference voltage Vt generated by the constant voltage generating circuit 13.
Please refer to FIG. 3A and FIG. 3B. FIG. 3A is a diagram of signal waveforms of the driving circuit in FIG. 1 operated at odd field (negative polarity period). FIG. 3B is a diagram of signal waveforms of the driving circuit in FIG. 1 operated at even field (positive polarity period).
As shown in FIG. 3A, while the driving circuit is operated at odd field, or the LCD cell is driven at negative polarity, the gate controlling signal Vg(N) is changed from a low voltage Vgl to a high voltage Vgh and is held for a time period Ts1 after the polarity of the video signal Vsig is changed from positive to negative. Then the gate controlling signal Vg(N) will be lowered to a negative expiatory voltage Ve(xe2x88x92) and be held for a time period Ts2. After the gate controlling signal Vg(N) is lowered to the negative expiatory voltage Ve(xe2x88x92), a gate controlling signal Vg(N+1) at a succeeding scanning channel is changed from a low voltage Vgl to a high voltage Vgh and is held for a time period Ts1. Then the gate controlling signal Vg(N+1) will be lowered to a positive expiatory voltage Ve(+) and be held for a time period Ts2. The time period Ts2 is longer than the time period Ts1 in this example. After the time period Ts2 of holding the voltage, the gate controlling signal Vg(N) in a scanning channel will be returned to the low voltage Vgl from the negative expiatory voltage Ve(xe2x88x92), and the gate controlling signal Vg(N+1) in a succeeding scanning channel will be returned to the low voltage Vgl from the positive expiatory voltage Ve(+).
Similarly, as shown in FIG. 3B, while the driving circuit is operated at even field, or the LCD cell is driven at positive polarity, the gate controlling signal Vg(N) is changed from a low voltage Vgl to a high voltage Vgh and is held for a time period Ts1 after the polarity of the video signal Vsig is changed from negative to positive. Then the gate controlling signal Vg(N) will be lowered to a positive expiatory voltage Ve(+) and be held for a time period Ts2. After the gate controlling signal Vg(N) is lowered to the positive expiatory voltage Ve(+), a gate controlling signal Vg(N+1) at a succeeding scanning channel is changed from the low voltage Vgl to the high voltage Vgh and is held for a time period Ts1. Then the gate controlling signal Vg(N+1) will be lowered to the negative expiatory voltage Ve(xe2x88x92) and be held for a time period Ts2. The time period Ts2 is longer than the time period Ts1 in this example, that is, the gate controlling signal Vg(N+1) accomplishes its scanning while the gate controlling signal Vg(N) is at the positive expiatory voltage Ve(+). After the time period Ts2, the gate controlling signal Vg(N) in a scanning channel will be returned to the voltage Vgl from the positive expiatory voltage Ve(+), and the gate controlling signal Vg(N+1) in a succeeding scanning channel will be returned to the voltage Vgl from the negative expiatory voltage Ve(xe2x88x92).
While the reference voltage Vt is constant, the driving method in FIG. 3A and FIG. 3B utilizes a 4-level gate signal combined with a C-coupled effect induced by parasitic capacitors and the storage capacitor to keep the voltage of the pixel electrode A of a LCD cell in the voltage range for positive driving or negative driving.
FIGS. 4A, 4B, 5A, and 5B show diagrams of signal waveforms of the driving circuit in FIG. 1. Although the output voltage range of the video signal Vsig can be constricted by the method utilizing a 4-level gate signal, the waveforms of the gate controlling signal Vg(N) and Vg(N+1) are very complicated.
FIG. 6 is a diagram of signal waveforms utilizing a 3-level gate signal of the driving circuit in FIG. 1. The waveforms of this driving method with 3-level gate signals are less complicated. However, this method is achieved by the enlargement of the output voltage range of the video signal Vsig. Thus, the cost of the video signal driving circuit 12 is higher.
Therefore, an object of the present invention is to provide a driving method for a liquid crystal display (LCD). The present invention utilizes the coupling effect of the parasitic capacitors and the storage capacitor to keep the voltage of the pixel electrode A of a LCD cell in the voltage range of positive driving or negative driving. Further, the waveforms of the gate controlling signals are simplified and the output voltage range of the video signal Vsig is constricted.
In the present invention, the LCD is driven by a plurality of switching transistors, such as TFTs, positioned in a matrix. Each switching transistor comprises a drain, a gate and a source. The drain of each switching transistor couples to a first scanning signal via a storage capacitor and to a pixel electrode. The gate and the source of each switching transistor respectively couple to a second scanning signal and a video signal. One step of the driving method of the present invention is shifting the video signal to have a dc voltage of a first predetermined voltage. Another step is adding a second predetermined voltage to the pixel electrode after the second scanning signal changes the state of the switching transistor from turned-on to turn-off.
The first predetermined voltage is equal to
xe2x88x92V*+[Cgd/Ct]xc3x97Vg.
V* is the central driving voltage of the LCD. Cgd is a gate-to-drain parasitic capacitance formed between the gate and the drain of each TFT. Ct comprising Cgd is a totally effective capacitance at the pixel electrode. Vg is the voltage pulse height at the second scanning signals.
The second predetermined voltage is equal to 2xc3x97V*. A further equation exists between the second predetermined voltage and the capacitors; that is
Vge(xe2x88x92)xc3x97Cs/Ct=2xc3x97V*.
Vge(xe2x88x92) is a negative gate expiatory voltage. Cs is the capacitance of the storage capacitor. Ct is a totally effective capacitance at the-pixel electrode. V* is the central driving voltage of the LCD.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.